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Who Am I ?

 

My name is Jean-Philippe Lambert (AKA JPL on Func_ forum), I’m french (that can explain why my english is not really “good”)... I was born in north-east of France, I’m married, and I have two daughters. I did all my studies in north-east of France, and I obtained a PhD in micro electronics in 1999. After one year of consulting, my wife and I, decided to move to south of France. The main reason was my job (I was on the road all week), and the birth of my first daughter: I wanted to see my little baby growing up... On top of that, it was a very good idea in term of “windsurfing trip”... North-east of France has few good spots, and riding during autumn and winter (when there is really wind) is a real challenge due to the very cold weather...

I’m also a FPS fan from years ago... I started with Wolfenstein and Doom... Then I discovered Quake, and as an obvious thing, I was thinking of mapping, but didn’t find time for... And some years ago (by the end of 2003 exactly), I found QuArK editor, and Func_ forum at the same time... and so I decided to start mapping: and it’s now a real hobby...

 

Here follows my professional CV. Please note I’m not currently looking for a new job, but I’m always open to discuss about “good opportunities”...

 

My Professional CV

 

Jean-Philippe LAMBERT

lambert_jph@yahoo.fr

Born in 1970, the 20th of March

Married, 2 children

Bluetooth System Architect / Electronic Design Engineer

 

PhD of Metz University and SUPELEC in Micro-Electronics (France - 1999)

“Optimization and digitalization of a digital modem radio frequency stage for high rate applications on TV cable”

 

SUMMARY:

I am a hardware engineer with 10+ years experience in RTL coding, 5 years experience in Bluetooth IP/product development, and 4 years in Bluetooth system architecture specification. For the last 5 years I’ve been working as principal design engineer, technical leader and system architect for Wipro - NewLogic, a leading semiconductor design services provider and supplier of intellectual property (IP) cores for complex wireless and wireline applications. During this time I’ve been a member of the Bluetooth SIG Core Specification Working Group. I specified and designed implementation solutions for Bluetooth controller, ensured development flow process respect, worked with local and foreign business partners and customers, ensuring pre-sales activities and customer support, accommodating the necessary design changes in order the end-product to be successful. I have an expert knowledge in digital design flow methodologies, design simulation, and full system validation. I have a proven Bluetooth system architecture expertise. I am self-motivated, and an enthusiastic person with strong communication skills. I am not afraid to make decisions and take responsibility. I like to work on complex systems, to solve problems, and I’m able to work in multitasking mode. I am always willing to learn new technologies and perform self-education every day.

 

SPECIALTIES:

Bluetooth Low Energy system architecture

Bluetooth 3.0 + HS system architecture

Bluetooth 2.1 + EDR system architecture

Matlab

Clock / Reset / Power Gating Strategy

VHDL / Verilog RTL design

DFT / BIST / ATPG

Simulations

Synthesis / STA

Formal Verification

FPGA Prototyping

Back-End knowledges (X-talk, IR-DROP, Metal Filling, etc...)

 

GENERAL SKILLS:

10 years of experience in digital development

         - RTL Design / DFT / Simulation / Synthesis / ATPG / FPGA prototyping with various tools and platform

         - Back-end flow knowledge (Clock Tree insertion / X-talk / Metal filling / etc..)

         - Power Gating Strategy / Clock - Reset Controller Specialist

4 years of experience in Bluetooth system

         - Bluetooth SIG CSWG member for 16 months

         - Bluetooth 1.2/2.0/2.1 development

         - Bluetooth 3.0+HS architecture knowledge

         - Bluetooth Low Energy development

Technical lead of a digital design team (up to 6 members)

Ability to work with team and customers from different locations (e.g: India, Germany, US, China, Israel, etc..)

Native french, good english, and scholastic spanish

 

PROFESSIONNAL EXPERIENCES:

From January 2010: RivieraWaves, Sophia Antipolis - France

Bluetooth System Architect and co-Founder

Bluetooth Low Energy IP development

Customer supports.

Pre-sales activities.

 

From October 2004 to October 2009: WiPro - NewLogic Technologies, Sophia Antipolis - France

Bluetooth System Architect / Principal Design Engineer role for 2 years

Bluetooth SIG Core Specification Working Group Member from January 2008 to April 2009.

Bluetooth 3.0 + HS Implementation pre-study

Bluetooth Low Energy Implementation pre-study

Bluetooth 2.1 RF / Modem IP and SoC development (90 nm technology): Specifications / Matlab / Design Lead

Bluetooth 2.1 Baseband Controller IP development: Specifications / Design Lead / Validation plan

Bluetooth 2.0 Baseband Controller IP development: Specifications / Design Lead

Bluetooth 1.2 Baseband Controller IP improvement: Design / Simulation / FPGA Prototyping

Wild RF Eagle (WiFi RF / Modem) SoC development (0.18 µm technology): Design / Simulation 

Agere VX400 GSM Multimedia Platform prototyping: Specific FPGA design / Simulation / FPGA prototyping / system testing.

 

From October 2002 to October 2004: THALES Microelectronics, Sophia Antipolis - France. / Senior Consultant.

     - Project in Texas Instruments - Villeneuve-Loubet, France

OMAP2430-2140 (GSM platform SoC) project in IP BU Team: PRCM (Power, Reset, and Clock Module): Design / DFT / Simulation / Synthesis / ATPG, and Formal Verification

 

    - Project in NewLogic Technologies - Sophia antipolis, France

WildChip / ColdFire projects (Modem 802.11a,b,g / 0.18 µm technology), and Jupiter project (Modem 802.11a,b,g / CMOS 90 nm): Design, Gate-level Simulation, Code Coverage, Synthesis, and FPGA prototyping

 

    - Project in StepMind- Le Cannet - France

Balsa0 / Balsa1 projects (802.11/WiFi, Hyperlan and Hyperlan2 Modem / 0.18 µm technology): Design / Simulations / Code Coverage / Synthesis / ATPG / Formal Verification

 

From January 2002 to September 2002: TACHYS Technologies, Sophia Antipolis - France. / VHDL Designer

3.2 Gbits/s serial link IP, XGXS interface development (XGMII to XAUI : 10 Gbits/s 802.3 Ethernet link), Infiniband 1x repeater and PCI Express serial link development, 0.18 µm / 0.13 µm technology: Design / Simulation / Synthesis / Test board development / FPGA prototyping.

 

From November 2000 to January 2002: ALTIOR Sophia Antipolis – France / Senior Consultant.

    - Project in TACHYS Technologies, Sophia Antipolis - France

SERDES, 10Gbit Ethernet, InfiniBand, PCI Express IPs provider

 

    - Project in PHILIPS Semiconductors, Sophia Antipolis - France

Blueberry project (Bluetooth Base-Band Controller): Design / Simulations / Synthesis / Formal Verification.

 

From July 1999 to November 2000: ALPLOG Strasbourg – France / Junior Consultant.

    - Project in XEIKON / NIPSON, Belfort - France

High Speed Industrial Printer development: Board Schematic / Place and route document / FPGA implementation / Board Bring-Up and Test / Printer tests.

 

From June 1995 to July 1999: University of Metz / ENSEM / SUPELEC, France / PhD Student.

    - I&TCOM society partnership for EURICO European project:

    - Applied research in LICM/CLOES SUPELEC laboratory:

    - Teaching for University of Metz and ENSEM

 

FOREIGN LANGUAGES

French:          Native.

English:          Good.

Spanish:         Scholastic.

 

OTHERS

French driving license.

Tennis, swimming, soccer and windsurf practice.